To avoid interference among adjacent integrated circuit devices, it is desirable to utilize an isolation technique to electrically and/or structurally isolate the devices and conductive lines associated therewith. To increase integration density, it is desirable to reduce not only the dimensions of the discrete devices, but also the area and width of isolation regions between the devices. How the isolation regions are formed may limit integration density, may affect the reliability of the devices, and/or may affect the performance of the devices.
Trench isolation techniques, including shallow trench isolation (STI) techniques, are widely used to isolate integrated circuit devices. A trench isolation technique can include forming a hard mask pattern that exposes field regions and covers active regions of a semiconductor substrate. The exposed field regions can be etched using the hard mask pattern as an etching mask to form trenches in the semiconductor substrate. The trenches can then be filled with an insulating material to form an isolation structure between devices.
However, as integration density is increased, it may be desirable to reduce the pitch of the hard mask pattern and to narrow the associated widths of the trenches formed in the field regions. Consequently, the aspect ratio of the height divided by the width of the trenches typically increases with increased integration density. It can become increasingly difficult to fill narrow trenches having a high aspect ratio, which may lead to unwanted voids and discontinuities in the insulating regions.